library ieee;
use ieee.std_logic_1164.all;

entity TFlipFlop is
	port (
		clk, clr_al : in bit;
		t : in bit;
		q : out bit
	);
end entity TFlipFlop;

architecture dataFlow of TFlipFlop is
	signal temp_q : bit := '0';
begin
	B1 : block ((clk = '1') AND (NOT clk'stable))
	begin 
		temp_q <= guarded ((not temp_q) and clr_al) when t = '1' else (temp_q and clr_al);
	end block;
	q <= temp_q;

end architecture dataFlow;